Algorithms implemented in digital data processing systems, such as a programmable micro processor and a digital signal processor (DSP), may use a part of a memory as a buffer to store or read operation results. As shown in FIG. 1, temporal operation results generated during implementation of algorithms are written to a buffer memory in the form of bit streams, such as 8-bit streams, 16-bit streams, 32-bit streams, or 64-bit streams. Under the control of a microprocessor, such data bit streams may be transferred to another address of the buffer memory or are read for use in another operation.
In an ordinary memory without considering the operation of a cache memory, data is written to or read from a valid address without the occurrence of a miss or hit, as shown in FIG. 2A. However, when a memory system uses a cache memory as a buffer, data transmission to an off-chip memory may result from a cache miss as shown in FIG. 2B. This may cause degradation in the performance of the entire memory system. In addition, in a write-back operation of the cache memory, when data that has been written at least once is replaced in the cache memory, data transmission to the off-chip memory may be unnecessary. General operations of cache memories are described, for example, in U.S. Pat. No. 6,470,443, the disclosure of which is hereby incorporated herein by reference.
FIGS. 3A and 3B are diagrams that illustrate operations for handling cache misses in a write-back write-allocate cache memory. It is assumed that a buffer size is N. This type of cache memory, as shown in FIG. 3A, causes a cache miss while an initial write operation is performed on a buffer, thereby reading out N bytes of data from an off-chip memory. The operating speed of the entire memory system may decrease due to the off-chip memory access. Moreover, this may result in relatively high power consumption. Also, as shown in FIG. 3B, data updated by the write operation is transmitted to the off-chip memory in the end when the replacement is made. Similarly operating speed of the entire memory system may decrease due to the N byte data transmission and may also result in relatively high power consumption.
FIG. 4 is a diagram that illustrates operations for handling cache misses in a write-through write-no allocate cache memory. It is assumed that the buffer size is N bytes. In this type of cache memory, as shown in FIG. 4, a bus is occupied in the first N-byte data write operation, data in the off-chip memory is updated, and an access to the N-byte data in the off-chip memory occurs in a later read operation. The operating speed of the entire memory system may decrease due to the access of the off-chip memory and a relatively large amount of power may be consumed. In other words, cache memories may require an access to 2N-bytes of data in the off-memory chip, which may degrade system performance and may increase power consumption.
A part of the cache memory may be used for a buffer, like a static random access memory (SRAM). In this case, however, an address and a size of a storing place of the cache memory used for the buffer may be fixed. As a result, the cache memory may not be used as efficiently.